DICA LAB

Wednesday, July 30, 2008

syllabus

1. simulation of logic gates using VHDL

2. simulation of half-adder & full-adder

3. simulation of D-flip flop


4. simulation of 3-8 decoder


5. simulation of 16:1 multiplexer using 74151


6. simulation of 16:1 multiplexer using 74150


7. simulation of 4 bit comparator


9. simulation of ALU (74381)


10. simulation of decade contact


11. simulation of 4 bit counter


12. simulation of 32 bit one's counter


13. simulation of universal shift register


14. simulation of priority & coded
Posted by raj at 10:15 AM

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