Typical Combinational Components

Typical Combinational Components

The following behavior style codes demonstrate the concurrent and sequential capabilities of VHDL. The concurrent statements are written within the body of an architecture. They include concurrent signal assignment, concurrent process and component instantiations (port map statement). Sequential statements are written within a process statement, function or procedure. Sequential statement include case statement, if-then-else statement and loop statement.

Multiplexor	Behavior Code	Test Bench	Behavior Simulation	Synthesis Schematic	Gate-level Simulation
Decoder	Behavior Code	Test Bench	Behavior Simulation	Synthesis Schematic	Gate-level Simulation
Adder	Behavior Code	Test Bench	Behavior Simulation	Synthesis Schematic	Gate-level Simulation
Comparator	Behavior Code	Test Bench	Behavior Simulation	Synthesis Schematic	Gate-level Simulation
ALU	Behavior Code	Test Bench	Behavior Simulation	Synthesis Schematic	Gate-level Simulation
Multiplier	Behavior Code	Test Bench	Behavior Simulation	Synthesis Schematic	Gate-level Simulation